Technical Field
The present invention relates to semiconductor processing, and more particularly to devices and integration methods for different material fins on a same semiconductor-on-insulator substrate (SOI).
Description of the Related Art
Many semiconductor devices employ fin structures for the formation of the field effect transistors (finFETs). In conventional fin formation processes, a bulk silicon substrate is etched, and a SiGe layer is grown. Later, each portion is etched to form fins. N-type field effect transistors (NFETs) are formed in the silicon and P-type field effect transistors (PFETs) are formed in the SiGe material.
In some instances, the use of SiGe fins is advantageous due to improved mobility; however, SiGe structures formed epitaxially may be limited by critical thickness. For example, if the thickness of the epitaxial layer is kept small enough to maintain its elastic strain energy below an energy of dislocation formation (defects), the strained-layer structure will be thermodynamically stable against dislocation formation. To maintain a defect free epitaxial layer, the thickness of the layer is limited.
In SiGe, this critical thickness depends strongly on Ge concentration in the layer. In complementary metal oxide semiconductor (CMOS) processing, conventional methods include a Si fin being etched to leave only a 5-10 nm layer of Si on a PFET side. A SiGe layer is epitaxially grown on the Si layer. Since the critical thickness depends on the Ge content, only a 5-10 nm SiGe layer can be epitaxially grown in a blanket growth process that is fully strained without defects for a desired Ge concentration in the SiGe layer.